1. Field of the Invention
The present invention relates to Electrostatic Discharge Protection (ESDP) devices. In particular, the present invention relates to Metal-Oxide-Silicon (MOS) transistors used to provide ESDP, including, but not limited to, N-type MOS transistors. More particularly, the present invention relates to the introduction of a tailored low-density drain (LDD) region of such MOS transistors to provide sufficient insulative characteristics without reliance upon standard field oxide isolation.
2. Description of the Prior Art
The fabrication of increasingly smaller integrated circuit (IC) devices has made the reliance upon effective smaller ESDP devices more important. It is well known that transient voltage surges, referred to as electrostatic discharges that may be thousands of volts, commonly occur at the input/output terminals of IC's. These terminals are electrically coupled to active circuit components including, but not limited to, bipolar and MOS transistors. It is important to block ESD events or to divert ESD events away from the gates of transistors, particularly those transistors acting as circuit buffers, in order to ensure that the transistors are not destroyed or otherwise compromised. When that occurs, operation of the circuit can be adversely affected, including the possibility of system failure.
As ESD problems are widespread, wide arrays of solutions have been developed. For the most part, these solutions have involved the addition of low-breakdown transistors or diodes placed between the input/output and buffer so as to divert the ESD's away from the buffer. That is, the transistor or diode is designed to be non-conducting under expected potential values, and conducting when a potential on an input or output buffer node exceeds those expected values. When turned on by the higher-than-expected potential, the ESD device diverts current associated with such transient conditions away from the critical buffer node. Commonly, it is desirable to have the transient current diverted to a low-potential power rail, generally defined as ground. N-type MOS (NMOS) transistors are used to achieve that end.
More recently, pluralities of NMOS transistors have been employed in parallel combination to provide protection. However, it is important in such a configuration to make sure that each of the "fingers" of the combination turns on at substantially the same time. Failure to do so will result in the first of the transistors in the set to turn on to support the entire transient load. That generally causes failure of that transistor unit as well as the entire ESD protection device. Ballast resistance is required in these devices as a means to alleviate problems of non-simultaneous turn-on; however, the ballast that is often required can lead to unacceptable increases in transistor set size. Variations occurring during processing of the prior ballasted ESD devices further tend to yield unreliable ESD protection, particularly where vertical pathways and field oxides were relied upon to provide the resistance. It is well known that such pathways can vary substantially in resistance from one site to another.
While tremendous effort is made to make the fabrication of semiconductor devices as accurate as possible, there will remain vagaries in active device characteristics from one production run to another and even within production runs. Given the size of the devices currently being made, the problems associated with any vagaries in, for example, doping levels, doping depths, alignment, and the like, are amplified. It is therefore important to isolate distinct active areas as much as possible so that the deficiencies in one area will not automatically affect adjacent active areas detrimentally. In prior fabrication processes, isolation regions could be made relatively large. One such type of isolation region, the field oxide, is introduced substantially at the surface of a semiconductor wafer between active areas. The field oxide is dopant deficient such that it is a poor conductor with respect to the active areas of the fabricated semiconductor product. However, as earlier indicated, that doping level can vary considerably.
The isolating field oxide regions, as well as other isolation and active areas, are formed as part of an integrated fabrication process. The process includes a series of "mask" steps highlighted by the application of photoresistant materials used to define the boundaries of regions of semiconductor material to be etched or implanted with dopant material. Of course, pursuant to the desire to make increasingly smaller systems, it is a goal to tightly control and minimize structure dimensions. It is also a goal to place active elements at or near the surface of the structure. Achievement of at least these two goals results in faster, more reliable, integrated circuits requiring less power to operate than prior-art circuits.
Present advanced fabrication techniques provide bipolar and MOS transistor structures, including NMOS transistors for use as ESDP devices, with these desired characteristics. One fabrication process found to be particularly useful in forming desired MOS integrated circuits, including NMOS and P-type MOS (PMOS) transistors, is summarized in the following table of mask steps.
______________________________________ Mask No. Mask Function ______________________________________ 1.0 Retrograde NWell Definition Mask 2.0 Retrograde PWell/Channel Stop Definition Mask 3.0 Isolation Oxide Definition Mask 4.0 MOS Active Area Definition Mask 5.0 Active Strip Mask 6.0 Poly Gate Definition Mask 7.0 N LDD Mask 8.0 P LDD Mask 9.0 Silicide Exclusion Mask 10.0 P.sup.+ Source/Drain Definition Mask (PMOS) 11.0 N.sup.+ Source/Drain Definition Mask (NMOS) 12.0 MOS Contact Definition Mask 13.0 METAL 1 (M1) Definition Mask 14.0 METAL 2 (M2) Definition Mask ______________________________________
While there are many steps and stages associated with the complete fabrication of an integrated circuit on a semiconductor wafer, the ones set out above and described briefly herein are directly applicable to the present invention. Initially, in regard to making the PMOS and NMOS structures, an "NWell" and a "PWell" are first created on a P type substrate of semiconductor material, using conventional fabrication sequences. This is accomplished by introducing, such as by implantation, respectively, an N concentration of relatively fast-diffusing N type atoms to form an NWell "bed" for the PMOS structure, and a P concentration of relatively fast-diffusing P type atoms to form a PWell "bed" for the NMOS structure. After NWell and PWell bed introduction into the substrate, an epitaxial layer in the form of single crystal N type semiconductor material in an N-concentration is formed over both well beds. Prior integrated circuit fabrication techniques involved the formation of epitaxial layers with charge carrier doping levels on the order of 1-3.times.10.sup.16 atoms/cc. The present fabrication process summarized above for sub-micron devices involves the formation of the epitaxial layer with a charge carrier doping level of about 1-3.times.10.sup.15 atoms/cc.
Subsequent conventional diffusion processing drives the NWell and PWell atoms in retrograde concentrations to the surface of the epitaxial layer. Isolation oxide layers are formed about the MOS transistor structures by conventional mask, etch, and formation sequences so as to isolate them from adjacent structures. The field oxide regions are formed are formed above the isolation regions using a field oxide region definition mask in order to further isolate adjacent structures. Channel stop regions, formed at the same time and of the same atom type as the PWell, underlie the isolation oxide regions surrounding both the retrograde NWell and retrograde PWell. The channel stops isolate the wells from parasitic MOS effects caused by adjacent structures.
Formation of the completed MOS transistor structures requires the fabrication of the gate, source, and drain components of the NMOS and PMOS transistor structures. The gates are formed of a polycrystalline layer of semiconductor material, using a well-known mask, etch, and deposition sequence. These "poly gates" are formed on the surface of the respective wells, but are separated from the well surfaces by an underlying gate oxide layer. This gate oxide layer acts as a dielectric, insulating the gate of the particular MOS transistor structure from the source, the drain, and the channel lying therebetween.
After poly gate formation, a sealing oxide is formed on the surface of the gates and on the active regions of the MOS wells. This thermally-grown sealing oxide protects the gates and CMOS wells during subsequent "lightly-doped drain" (LDD) implantation steps. It is also part of the architecture that provides for "self-alignment" of the soon-to-be-formed source and drain regions of the MOS transistors.
The next phase of MOS transistor development involves the formation of the source and drain regions. Initially, a relatively fast-diffusing N type atom in an N concentration is shallowly implanted in the surface of the PWell and a relatively fast-diffusing P type atom in an N concentration is shallowly implanted in the surface of the NWell. These initial implants are designed to extend slightly beyond the final dimensions of the source and drain regions, resulting in an effective gate channel length in the range 0.4-0.6 micron. The purpose of this initial implant is to minimize hot electron effects in the transistor channel region. The initial implant procedure includes the formation of the N LDD and P LDD regions in both transistor types. In addition to initiating the formation of the well-defined source and drain regions, the shallow LDD also provides a gradual transition from source or drain to the channel region, thereby reducing hot electron effects. Of course, with the much smaller structures fabricated today, the importance of the LDD in reducing hot electron effects increases. The LDD regions are less heavily doped than the specific source and drain regions, but more heavily doped than the insulative oxide regions immediately adjacent to the active areas. It is this portion of the fabrication process that is related to the creation of the ESDP transistor of the present invention.
In order to produce shallower, and therefore faster, devices, and properly sized source and drain regions, a spacer oxide is deposited to a thickness of about 2000 .ANG. over the future source and drain regions and the poly gates. The spacer oxide is then etched to expose substantially all of the active areas of the device during the silicide exclusion step. Etching of the spacer oxide exposes the top of the gate and the subsequent source and drain regions for following ion implants and metal deposition. However, at the sides of the built-up area associated with the gates, the spacer oxide layer is significantly thicker than in the other areas. As a result, the etching sequence leaves sealing material in place at the sides of the gate. This is beneficial in subsequent ion implanting in that the gate-side sealing layer blocks such implants, leaving the LDD region ion levels fixed throughout the process for purposes earlier noted regarding hot electron effects. The gate-side sealing layer also acts as one portion of the means for ensuring self-alignment of the active areas that are to become the source and drain regions.
Following the sealing layer etching process, relatively slow-diffusing P type atoms in a P.sup.+ concentration in the surface of the NWell and relatively slow-diffusing N type atoms in an N.sup.+ concentration are introduced into the surface of the PWell, using conventional mask, etch and implant sequences, to define the source and drain regions of the PMOS and NMOS transistor structures respectively. However, the implant does not occur in the active area immediately adjacent to the gate, due to the remaining gate-side sealing layer that acts as an implant blocker. Subsequent annealing drives the slow-diffusing atoms to pre-defined depths in the respective wells. Fabrication steps well known in the field provide the necessary contact sites, insulative surface regions, and metal conductors to complete the formation of the PMOS and NMOS transistors.
A preliminary conduction layer is defined by a metal-silicon combination identified as a silicide layer that provides a smooth transition between silicon-based layers of the active area and metal contacts. To the extent that it is possible to maintain the silicide layer proximate to the poly gate in light of the gate-side sealing layer, it is important to do so in order to lower the sheet resistance of the gate. However, prior attempts at improving ballast resistances in ESD protection devices have come at the expense of modifying the silicide layer and thereby impairing optimization of gate operation. In any event, in the general processing scheme, conventional bond pads that are the metal contacts are formed in order to couple the transistors to external circuitry, including by way of input/output nodes.
The advance fabrication process described above, particularly related to the self-alignment of source and drain regions using poly gates, and the LDD doping, can be utilized to form a transistor device that solves ESD problems in the manner previously noted. However, in standard fabrication processes of the type described, there are steps taken to enhance transistor action that adversely affect ESDP capability. Specifically, conductive materials added to the surface of the structure adjacent to the source and drain regions reduce the resistance associated with those areas and thereby improve the transistor's operational characteristics. However, it is also important to provide series resistance between adjacent regions of the transistor structure in order to provide effective ESD protection. These contrasting goals can result in a compromise of transistor operation and ESD protection. Attempts to modify the effect of silicide layers at the transistor active region surfaces by reducing the ion concentration at the source and drain will increase resistance and therefore will be beneficial in an ESD protection device. However, this advance is offset by a reduction in transistor performance.
Prior attempts to improve ballast resistance for ESD transistors have been directed to modification of either the N+ implant step or the NWell formation step. In both instances, it is necessary to create very large active areas in order to produce satisfactory resistances of on the order of 50-100 .OMEGA.. It is well known that fabrication vagaries associated with active semiconductor device formation may yield lower than desired sheet resistances and limitations on available active area. These are two undesirable side effects of creating ballast resistance during either NWell or N+ source/drain formation.
U.S. Pat. No. 5,493,142 issued to Randazzo et al. describes one approach to formation of an ESD protection device. The LDD dopant procedure taught by Randazzo results in a penetration of the dopant into the channel underlying the gate. This has been determined to reduce by half the current carrying capability of the device during an ESD event. Further, the LDD reduces the peak electric field, slowing the ESD device's response. Such a limitation is undesirable. Yet further, and as alluded to herein, the Randazzo process provides for placement of the silicide exclusion mask edge on the gate. This can produce an increase in the sheet resistance of the gate that will be variable as a function of the lack of control in alignment to the gate edge.
U.S. Pat. No. 5,498,892 issued to Walker et al. describes another approach to formation of ballast resistance, in which selected portions of the drain region of an NMOS transistor are blocked with photoresist from the N+ mask step. However, the fabrication process utilized by Walker does not include the application of silicide, which is needed for enhanced transistor action. The Walker ballast resistor process therefore does not address a method that includes the use of silicide and therefore does not address the need to exclude silicide in the drain of an ESD device while allowing silicide on other circuitry.
Therefore, what is needed is an ESD protection device that protects a node while maintaining sufficient and well-controlled resistance characteristics, including the "fingers" of an ESD-protection transistor set, so that activation is reliable. What is also needed is such a protection device that maintains such resistance with increase to the overall size of the active area. Further, what is needed is an ESD protection device that can be fabricated with minimal intrusion on existing fabrication processes, namely, requiring extra masks. Finally, what is needed is such a device that provides adequate ESD protection with minimal compromise of the basic transistor structure's functional performance.